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Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /LPSPI /SPI_ICR

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Interpret as SPI_ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ICR)ICR

Description

Interrupt Clear Register

Fields

ICR

Clear Interrupts. This bit is set if any of the interrupts below are active. A read clears the Transmit FIFO Overflow, Receive FIFO Underflow, Receive FIFO Overflow, and Multi-Master Contention interrupts. Writing to this bit has no effect.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data